Due to continuing improvements in fabrication processes and design tools, and to demands for ever greater functionality in packages of limited volume, it has become commonplace to design and market application-specific integrated circuits (hereafter, “ASICs”) of great complexity, including tens of millions of gates, or even more. In view of such demands, it has become attractive to consider three-dimensional (hereafter, “3D”) fabrication techniques, because such techniques have a known potential to improve performance and reduce power consumption, as well as to reduce package size.
Indeed, it is possible with 3D technology to partition functions on different levels, enabling a smaller area die with much higher yield to be fabricated separately and stacked at wafer level. 3D technology also enables heterogeneous integration of different device technologies (e.g., digital, analog, RF, MEMS, and photonics), and may allow the use of less costly fabrication processes due to increased logic densities in the overall stack. However, one possible drawback is that, depending on the 2D technology chosen for individual layers and the 3D assembly processes employed, 3D integration could increase the total device fabrication duration and costs.
The costs of fabricating highly complex ASICs and other integrated circuits have in fact driven a further trend toward designing IC platforms that include both standardized building blocks and programmable logic and interconnects. A field-programmable gate array (FPGA), for example, reduces non-recurring engineering (NRE) costs because at least some of its application-specific functionality is programmed by the user.
Another approach is the structured ASIC (hereafter, “sASIC”). The sASIC concept resembles the FPGA concept in that it employs a regular fabric-like circuit architecture in pre-qualified base array platforms to accelerate turn-around times and reduce NRE costs and development risk.
The fabrication sequence for a sASIC uses a one-time metal-via mask to configure user function into the base array. As with an FPGA, the sASIC base array can be pre-fabricated before customization and re-used across multiple design implementations, and it can be produced in significantly shorter time and at a much lower cost than a custom ASIC. The sASIC provides some advantage over FPGAs because it is generally more competitive to custom ASICs in speed, power, and circuit densities.
As the above-described trends converge, there is a growing need for new approaches to 3D integration that offer the cost reductions and other advantages of standardized base arrays combined with programmable building blocks.